With regard to conventional NAND-type memories, the high integration by miniaturization has been limited mainly due to the following reasons. The first reason is that a shorter channel length causes a phenomenon in which current tends to occur between a source and a drain even when the gate voltage is equal to or lower than a threshold voltage (i.e., a so-called short channel effect), thus resulting in a fluctuated threshold voltage. The second reason is that a source or a drain having a shallow junction is difficult to be formed. The third reason is that the hot electrons during writing (or during programming) are injected to a floating gate to cause the fluctuation in the threshold voltage of the transistor. The fourth reason is that the interference between cells is caused by the capacitive coupling between cells adjacent to each other for example.
FIGS. 33(A) and 33(B) are views showing the basic structure of a conventional NAND-type flash memory. FIG. 33(A) shows a plane pattern. FIG. 33(B) shows an equivalent circuit.
As shown in FIGS. 33(A) and 33(B), the conventional NAND-type flash memory 100 has a NAND string 102 that is composed of; series-connected NAND-type flash memory cells 104; a first select gate transistor 111 connected to one end of the flash memory cells 104; and a second select gate transistor 112 connected to the other end of the flash memory cells 104. The first select gate transistor 111 is connected to a source line. The second select gate transistor 112 is connected to a bit line.
Flash memory cells adjacent to each other have a capacitive coupling at a parasitic capacitance 116, thereby causing the interference between the flash memory cells 104. A current approach is that the first select gate transistor 111 and the second select gate transistor 112 have a channel length longer than that of the flash memory cells 104 to thereby avoid the hot electron injection.
In order to solve the limitation on the conventional NAND-type flash memory as described above, Non-patent Literature 1 discloses a vertical memory cell array using vertical memory cells having a higher integration degree than that of a two-dimensional integrated circuit. This vertical memory cell uses a floating gate structure for nonvolatile storage.
In the memory cell of the floating gate structure, a floating gate composed of poly Si has a barrier height of 3.15 eV. Thus, high reliability is obtained for storage and a high integration degree also can be obtained. However, neighboring cells (cells adjacent to each other in the vertical direction in particular) have capacitive coupling to cause an intercell interference, which makes it difficult to improve the writing rate of the memory cell.
Furthermore, various elements using charge trap vertical memory cells instead of the floating gate structure have been disclosed as BiCS (see Non-patent Literature 1 and Non-patent Literature 2), p-BiCS (see Non-patent Literature 3 and Non-patent Literature 4), and TCATCS (see Non-patent Literature 5).
However, the charge trap-type vertical memory cell has a disadvantage in the storage reliability. This disadvantage is due to that the storage by the charge trap-type memory cell is retained by the trap charges in the insulator and has a low barrier height of 1.0 eV for example. Furthermore, in the case of this conventional technique, it is difficult to suppress a short channel effect or form the shallow source or drain junction, thus has a difficulty in solving the disadvantage due to the hot electron injection during writing (or during programming). Furthermore, the control of the charge amount to be stored is difficult and the storage of a plurality of pieces of bit information in one memory cell is also difficult.